HD64F3039F18 Datasheet, PDF (217/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 8 16-Bit Integrated Timer Unit (ITU)
Table 8.1 ITU Functions
Item
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Clock sources
Internal clocks: φ, φ/2, φ/4, φ/8
External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently
General registers
GRA0, GRB0
(output compare/
input capture registers)
GRA1, GRB1
GRA2, GRB2
GRA3, GRB3
GRA4, GRB4
Buffer registers
—
—
—
BRA3, BRB3 BRA4, BRB4
Input/output pins
Output pins
Counter clearing
function
TIOCA₀, TIOCB₀ TIOCA₁, TIOCB₁ TIOCA₂, TIOCB₂ TIOCA₃, TIOCB₃ TIOCA₄, TIOCB₄
—
—
—
—
TOCXA₄,
TOCXB₄
GRA0/GRB0 GRA1/GRB1 GRA2/GRB2 GRA3/GRB3 GRA4/GRB4
compare match compare match compare match compare match compare match
or input capture or input capture or input capture or input capture or input capture
Compare 0
O
O
O
O
O
match
1
O
O
O
O
O
output
Toggle O
O
—
O
O
Input capture function O
O
O
O
O
Synchronization
O
O
O
O
O
PWM mode
O
O
O
O
O
Reset-synchronized —
—
—
O
O
PWM mode
Complementary PWM —
—
—
O
O
mode
Phase counting mode —
—
O
—
—
Buffering
—
—
—
O
O
Interrupt sources
Three sources Three sources Three sources Three sources Three sources
• Compare
match/input
capture A0
• Compare
match/input
capture A1
• Compare
match/input
capture A2
• Compare
match/input
capture A3
• Compare
match/input
capture A4
• Compare
match/input
capture B0
• Compare
match/input
capture B1
• Compare
match/input
capture B2
• Compare
match/input
capture B3
• Compare
match/input
capture B4
• Overflow
• Overflow
• Overflow
• Overflow
• Overflow
Legend:
O: Available
—: Not available
Rev.3.00 Mar. 26, 2007 Page 193 of 682
REJ09B0353-0300