HD64F3039F18 Datasheet, PDF (539/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 17 Power-Down State
17.4.3 Selection of Oscillator Waiting Time after Exit from Software Standby Mode
Bits STS2 to STS0 in SYSCR, and its DIV1 and DIV0 in DIVCR should be set as follows.
Crystal Resonator
Set STS2 to STS0, and DIV1 and DIV0 so that the waiting time (for the clock to stabilize) is at
least 7 ms. Table 17.3 indicates the waiting times that are selected by STS2 to STS0, and DIV1
and DIV0 settings at various system clock frequencies.
External Clock
Any value may be set.
Table 17.3 Clock Frequency and Waiting Time for Clock to Settle
Waiting
DIV1 DIV0 STS2 STS1 STS0 Time 18 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz 1 MHz Unit
0
0
0
0
0 8192 states 0.46
0
0
1 16384 states 0.91
0
1
0 32768 states 1.8
0
1
1 65536 states 3.6
1
0
0 131072 states 7.3
1
0
1 1024 states 0.057
1
1
— Illegal setting
0
1
0
0
0 8192 states 0.91
0
0
1 16384 states 1.8
0
1
0 32768 states 3.6
0
1
1 65536 states 7.3
1
0
0 131072 states 14.6
1
0
1 1024 states 0.11
1
1
— Illegal setting
1
0
0
0
0 8192 states 1.8
0
0
1 16384 states 3.6
0
1
0 32768 states 7.3
0
1
1 65536 states 14.6
1
0
0 131072 states 29.1
1
0
1 1024 states 0.23
1
1
— Illegal setting
1
1
0
0
0 8192 states 3.6
0
0
1 16384 states 7.3
0
1
0 32768 states 14.6
0
1
1 65536 states 29.1
1
0
0 131072 states 58.3
1
0
1 1024 states 0.46
1
1
— Illegal setting
: Recommended setting
0.51
1.0
2.0
4.1
8.2
0.064
1.02
2.0
4.1
8.2
16.4
0.13
2.0
4.1
8.2
16.4
32.8
0.26
4.1
8.2
16.4
32.8
65.5
0.51
0.65
1.3
2.7
5.5
10.9
0.085
1.4
2.7
5.5
10.9
21.8
0.17
2.7
5.5
10.9
21.8
43.7
0.34
5.5
10.9
21.8
43.7
87.4
0.68
0.8
1.0
1.3
2.0
4.1
8.2
ms
1.6
2.0
2.7
4.1
8.2
16.4
3.3
4.1
5.5
8.2
16.4 32.8
6.6
8.2
10.9 16.4 32.8 65.5
13.1
16.4
21.8
32.8
65.5 131.1
0.10
0.13 0.17 0.26 0.51
1.0
1.6
2.0
2.7
4.1
8.2
16.4
ms
3.3
4.1
5.5
8.2
16.4 32.8
6.6
8.2
10.9 16.4 32.8 65.5
13.1
16.4
21.8
32.8
65.5 131.1
26.2
32.8
43.7
65.5 131.1 262.1
0.20
0.26 0.34 0.51
1.0
2.0
3.3
4.1
5.5
8.2
16.4 32.8
ms
6.6
8.2
10.9 16.4 32.8 65.5
13.1
16.4
21.8
32.8
65.5 131.1
26.2
32.8
43.7
65.5 131.1 262.1
52.4
65.5
87.4 131.1 262.1 524.3
0.41
0.51 0.68 1.02
2.0
4.1
6.6
13.1
26.2
52.4
104.9
0.82
8.2
10.9 16.4 32.8 65.5
ms
16.4 21.8 32.8 65.5 131.1
32.8 43.7 65.5 131.1 262.1
65.5 87.4 131.1 262.1 524.3
131.1 174.8 262.1 524.3 1048.6
1.0
1.4
2.0
4.1
8.2
Rev.3.00 Mar. 26, 2007 Page 515 of 682
REJ09B0353-0300