HD64F3039F18 Datasheet, PDF (145/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

6.3.2 Bus Control Signal Timing
Section 6 Bus Controller
8-Bit, Three-State-Access Areas
Figure 6.3 shows the timing of bus control signals for an 8-bit, three-state-access area. Wait states
can be inserted.
φ
Address bus
Bus cycle
T₁
T₂
T₃
External address
AS
Read
access
RD
D₇ to D₀
Valid
Write
access
WR
D₇ to D₀
Valid
Figure 6.3 Bus Control Signal Timing for 8-Bit, Three-State-Access Area
Rev.3.00 Mar. 26, 2007 Page 121 of 682
REJ09B0353-0300