HD64F3039F18 Datasheet, PDF (323/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 9 Programmable Timing Pattern Controller
9.2.6 Next Data Register B (NDRB)
NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups
3 and 2 (pins TP₁₅ to TP₈)*. During TPC output, when an ITU compare match event specified in
TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The address of
NDRB differs depending on whether TPC output groups 2 and 3 have the same output trigger or
different output triggers.
NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Note: * Since this LSI does not have a TP₁₄ pin, the TP₁₄ signal cannot be output to the outside.
Same Trigger for TPC Output Groups 2 and 3
If TPC output groups 2 and 3 are triggered by the same compare match event, the NDRB address
is H'FFA4. The upper 4 bits belong to group 3 and the lower 4 bits to group 2. Address H'FFA6
consists entirely of reserved bits that cannot be modified and always read 1.
Address H'FFA4
Bit
Initial value
Read/Write
7
NDR15
0
R/W
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
3
NDR11
0
R/W
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Next data 11 to 8
These bits store the next output
data for TPC output group 2
Address H'FFA6
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
—
—
—
—
Reserved bits
Rev.3.00 Mar. 26, 2007 Page 299 of 682
REJ09B0353-0300