HD64F3039F18 Datasheet, PDF (462/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 14 RAM
14.3 Operation
When the RAME bit is set to 1, the on-chip RAM is enabled. This LSI can access the on-chip
RAM when addressing the addresses shown in table 14.1 in each operation mode. When the
RAME bit is cleared to 0 in modes 1, 3, and 5 (expanded modes), external address space is
accessed. When the RAME bit is cleared to 0 in modes 6 and 7 (single-chip modes), the on-chip
RAM is not accessed. Read operation always reads H'FF and disables writing.
The on-chip RAM is connected to the CPU by a 16-bit wide data bus and can be read and written
on a byte or a word basis.
Byte data can be accessed in two states using the higher 8 bits of the data bus. Word data
beginning from an even address can be accessed in two states using the 16-bit data bus.
Rev.3.00 Mar. 26, 2007 Page 438 of 682
REJ09B0353-0300