HD64F3039F18 Datasheet, PDF (337/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 9 Programmable Timing Pattern Controller
Example of Non-Overlapping TPC Output
(Example of Four-Phase Complementary Non-Overlapping Output)
Figure 9.7 shows an example of the use of TPC output for four-phase complementary non-
overlapping pulse output.
TCNT value
GRB
TCNT
GRA
H'0000
NDRA
95
65
59
56
95
65
Time
PADR
00
TP₇
95 05 65 41 59 50 56 14 95 05 65
Non-overlap margin
TP₆
TP₅
TP₄
TP₃
TP₂
TP₁
TP₀
• The ITU channel to be used as the output trigger channel is set up so that GRA and GRB are output
compare registers and the counter will be cleared by compare match B. The TPC output trigger
period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TIER to enable
IMFA interrupts.
• H'FF is written in PADDR and NDERA, and bits G1CMS1, G1CMS0, G0CMS1, and G0CMS0 are set in
TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.
Bits G1NOV and G0NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is
written in NDRA.
• The timer counter in this ITU channel is started. When compare match B occurs, outputs change from
1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed
by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRA.
• Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95...
at successive IMFA interrupts.
Figure 9.7 Non-Overlapping TPC Output Example (Four-Phase Complementary
Non-Overlapping Pulse Output)
Rev.3.00 Mar. 26, 2007 Page 313 of 682
REJ09B0353-0300