HD64F3039F18 Datasheet, PDF (368/710 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series

Section 11 Serial Communication Interface
Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain new transmit data when the MSB is transmitted.
Bit 2
TEIE
Description
0
Transmit-end interrupt requests (TEI) are disabled*
(Initial value)
1
Transmit-end interrupt requests (TEI) are enabled*
Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in
SSR, then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by
clearing the TEIE bit to 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1/0): These bits select the SCI clock source and
enable or disable clock output from the SCK pin. Depending on the settings of CKE1 and CKE0,
the SCK pin can be used for generic input/output, serial clock output, or serial clock input.
The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external
clock source is selected (CKE1 = 1). After setting the CKE1 and CKE0 bits, select the SCI
operating mode in SMR. For further details on selection of the SCI clock source, see table 11.9.
Bit 1
CKE1
Bit 0
CKE0
Description
0
0
0
1
Asynchronous mode
Synchronous mode
Asynchronous mode
Internal clock, SCK pin available for generic
input/output*¹
Internal clock, SCK pin used for serial clock output*¹
Internal clock, SCK pin used for clock output*²
1
0
Synchronous mode
Asynchronous mode
Internal clock, SCK pin used for serial clock output
External clock, SCK pin used for clock input*³
1
1
Synchronous mode
Asynchronous mode
External clock, SCK pin used for serial clock input
External clock, SCK pin used for clock input*³
Synchronous mode External clock, SCK pin used for serial clock input
Notes: 1. Initial value
2. The output clock frequency is the same as the bit rate.
3. The input clock frequency is 16 times the bit rate.
Rev.3.00 Mar. 26, 2007 Page 344 of 682
REJ09B0353-0300