MC9S12T64 Datasheet, PDF (81/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
System Configuration
System Clock Description
PARTIDL — Part ID Register High
Address Offset: $001B ⁽¹⁾
Bit 7
6
5
4
3
2
1
Bit 0
Read: ID7
ID6
ID5
ID4
ID3 ⁽²⁾
ID2 ⁽²⁾
ID1 ⁽²⁾
ID0 ⁽²⁾
Write:
Reset:
Refer to Table 17
—
—
—
—
= Unimplemented
1. Register Address = Base Address (INITRG) + Address Offset
2. Motorola use only for production control. This field may be changed. User program should not refer to this field as an iden-
tification number.
System Clock Description
The Clock and Reset Generator provides the internal clock signals for
the core and all peripheral modules. Figure 13 shows the clock
connections from the CRG to all modules. The gating condition placed
on top of the individual clock gates indicates the dependencies of
different modes (STOP, WAIT) and the setting of the respective
configuration bits. For example, a WAIT(SYSWAI) gating condition
states that when the SYSWAI bit is set, the correspondent gate will be
disabled during WAIT mode.
Consult the CRG section in page 271 for details on clock generation and
clock enabling conditions.
Table 18 summarizes the enabling conditions of specific modules
according to the MCU mode of operation. All modules listed in Table 18
cease operation when the MCU enters STOP mode.
System Configuration
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MC9S12T64Revision 1.1.1