MC9S12T64 Datasheet, PDF (497/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Analog to Digital Converter (ATD)
Register Descriptions
Table 87 Conversion Sequence Length Coding. (Continued)
S8C
S4C S2C
S1C
Number of Conversions per
Sequence
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
X
X
X
8
FIFO — Result Register FIFO Mode
If this bit is zero (non-FIFO mode), the A/D conversion results map
into the result registers based on the conversion sequence; the result
of the first conversion appears in the first result register, the second
result in the second result register, and so on.
If this bit is one (FIFO mode) the conversion counter is not reset at the
beginning or end of a conversion sequence; conversion results are
placed in consecutive result registers between sequences. The result
register counter wraps around when it reaches the end of the result
register file. The conversion counter value in ATDSTAT0 can be used
to determine where in the result register file, the current conversion
result will be placed.
Finally, which result registers hold valid data can be tracked using the
conversion complete flags. Fast flag clear mode may or may not be
useful in a particular application to track valid data.
1 = Conversion results are placed in consecutive result registers
(wrap around at end).
0 = Conversion results are placed in the corresponding result
register up to the selected sequence length.
FRZ1, FRZ0 — Background Debug Freeze Enable
When debugging an application, it is useful in many cases to have the
ATD pause when a breakpoint (Freeze Mode) is encountered. These
2 bits determine how the ATD will respond to a breakpoint as shown
in Table 88. Leakage onto the storage node and comparator
Analog to Digital Converter (ATD)
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MC9S12T64Revision 1.1.1