MC9S12T64 Datasheet, PDF (143/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Multiplexed External Bus Interface (MEBI)
External Pin Descriptions
Table 29 External System Pins Associated With MEBI (Continued)
Pin Name
PE5/IPIPE0/
MODA
PE4/ECLK
PE3/LSTRB/
TAGLO
PE2/R/W
PE1/IRQ
PE0/XIRQ
PK7/ECS
Pin Functions
Description
MODA
At the rising edge on RESET, the state of this pin is registered into the
MODA bit to set the mode.
PE5
General purpose I/O pin, see PORTE and DDRE registers.
IPIPE0
Instruction pipe status bit 0, enabled by PIPOE bit in PEAR.
PE4
General purpose I/O pin, see PORTE and DDRE registers.
ECLK
Bus timing reference clock, can operate as a free-running clock at the
system clock rate or to produce one low-high clock per visible access,
with the high period stretched for slow accesses. ECLK is controlled by
the NECLK bit in PEAR, the IVIS bit in MODE and the ESTR bit in
EBICTL.
PE3
General purpose I/O pin, see PORTE and DDRE registers.
LSTRB
Low strobe bar, 0 indicates valid data on D7-D0.
SZ8
In peripheral mode, this pin is an input indicating the size of the data
transfer (0=16-bit; 1=8-bit).
TAGLO
In expanded wide mode or emulation narrow modes, when instruction
tagging is on and low strobe is enabled, a 0 at the falling edge of E tags
the low half of the instruction word being read into the instruction
queue.
PE2
General purpose I/O pin, see PORTE and DDRE registers.
R/W
Read/write, indicates the direction of internal data transfers. This is an
output except in peripheral mode where it is an input.
PE1
General purpose input-only pin, can be read even if IRQ enabled.
IRQ
Maskable interrupt request, can be level sensitive or edge sensitive.
PE0
General purpose input-only pin.
XIRQ
Non-maskable interrupt input.
PK7
General purpose I/O pin, see PORTK and DDRK registers.
ECS
Emulation chip select
Multiplexed External Bus Interface (MEBI)
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MC9S12T64Revision 1.1.1