MC9S12T64 Datasheet, PDF (402/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
By setting TFMOD in queue mode, when NOVW bit is set and the
corresponding capture and holding registers are emptied, an input
capture event will first update the related input capture register with
the main timer contents. At the next event the TCn data is transferred
to the TCnH register, The TCn is updated and the CnF interrupt flag
is set. See Figure 73 in page 413.
In all other input capture cases the interrupt flag is set by a valid
external event on PTn.
1 = If in queue mode (BUFEN=1 and LATQ=0), the timer flags
C3F–C0F in TFLG1 are set only when a latch on the
corresponding holding register occurs.
If the queue mode is not engaged, the timer flags C3F–C0F
are set the same way as for TFMOD=0.
0 = The timer flags C3F–C0F in TFLG1 are set when a valid input
capture transition on the corresponding port pin occurs.
PACMX — 8-Bit Pulse Accumulators Maximum Count
1 = When the 8-bit pulse accumulator has reached the value $FF,
it will not be incremented further. The value $FF indicates a
count of 255 or more.
0 = Normal operation. When the 8-bit pulse accumulator has
reached the value $FF, with the next active edge, it will be
incremented to $00.
BUFEN — IC Buffer Enable
1 = Input Capture and pulse accumulator holding registers are
enabled. The latching mode is defined by LATQ control bit.
Write one into ICLAT bit in MCCTL (see page 396), when
LATQ is set will produce latching of input capture and pulse
accumulators registers into their holding registers.
0 = Input Capture and pulse accumulator holding registers are
disabled.
LATQ — Input Control Latch or Queue Mode Enable
The BUFEN control bit should be set in order to enable the IC and
pulse accumulators holding registers. Otherwise LATQ latching
modes are disabled.
MC9S12T64Revision 1.1.1
Enhanced Capture Timer (ECT)
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