MC9S12T64 Datasheet, PDF (502/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Analog to Digital Converter (ATD)
ATD Control
Register 5
(ATDCTL5)
This register selects the type of conversion sequence and the analog
input channels sampled. Writes to this register will abort current
conversion sequence and start a new conversion sequence.
Address Offset: $0085
Bit 7
Read:
DJM
Write:
Reset:
0
6
5
4
3
0
DSGN
SCAN
MULT
2
1
Bit 0
CC
CB
CA
0
0
0
0
0
0
0
Unimplemented or Reserved
Read: anytime
Write: anytime
DJM — Result Register Data Justification Mode
1 = Right justified mode.
0 = Left justified mode.
This bit controls justification of conversion data in the result registers.
See ATDDRx A/D Conversion Result Registers (ATDDR0–7) in page
510 for details.
DSGN — Signed/Unsigned Result Data Mode
1 = Signed result register data select.
0 = Unsigned result register data select.
This bit selects between signed and unsigned conversion data representation
in the result registers. Signed data is represented as 2’s complement. See
ATDDRx A/D Conversion Result Registers (ATDDR0–7) in page 510
for details.
Table 91 summarizes the result data formats available and how they
are set up using the control bits.
Table 92 illustrates the difference between the signed and unsigned,
left justified output codes for an input signal range between 0 and 5.12
Volts.
MC9S12T64Revision 1.1.1
Analog to Digital Converter (ATD)
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