MC9S12T64 Datasheet, PDF (472/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
The SS pin is normally an input which should remain in the inactive high
state. However, in the master mode, if both MODFEN bit and SSOE bit
are set, then the SS pin is the slave select output.
The SS output becomes low during each transmission and is high when
the SPI is in the idling state. If the SS input becomes low while the SPI
is configured as a master, it indicates a mode fault error where more than
one master may be trying to drive the MOSI and SCK lines
simultaneously. In this case, the SPI immediately clears the output buffer
enables associated with the MISO, MOSI (or MOMI), and SCK pins so
that these pins become inputs. This mode fault error also clears the
MSTR control bit and sets the mode fault (MODF) flag in the SPI status
register. If the SPI interrupt enable bit (SPIE) is set when the MODF bit
gets set, then an SPI interrupt sequence is also requested
NOTE: There is an errata information about the mode fault behavior. See
MC9S12T64 Errata Sheet for details.
When a write to the SPI data register in the master occurs, there is a half
SCK-cycle delay. After the delay, SCK is started within the master. The
rest of the transfer operation differs slightly, depending on the clock
format specified by the SPI clock phase bit, CPHA, in SPI control register
1 (see Transmission Formats).
Slave Mode
The SPI operates in slave mode when the MSTR bit in SPI control
register1 is clear. In slave mode, SCK is the SPI clock input from the
master, and SS is the slave select input. Before a data transmission
occurs, the SS pin of the slave SPI must be at logic 0. SS must remain
low until the transmission is complete.
In slave mode, the function of the serial data output pin (MISO) and
serial data input pin (MOSI) is determined by the SPC0 bit in SPI control
register 2 and the MSTR control bit. While in slave mode, the SS input
controls the serial data output pin; if SS is high (not selected), the serial
data output pin is high impedance, and, if SS is low the first bit in the SPI
data register is driven out of the serial data output pin. Also, if the slave
is not selected (SS is high), then the SCK input is ignored and no internal
shifting of the SPI shift register takes place.
MC9S12T64Revision 1.1.1
Serial Peripheral Interface (SPI)
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