MC9S12T64 Datasheet, PDF (276/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
External Pin Descriptions
Overview
This section lists and describes the signals that connect off chip.
Detailed Signal
Descriptions
VDDPLL, VSSPLL
XFC
Theses pins provides operating voltage (VDDPLL) and ground
(VSSPLL) for the PLL circuitry. This allows the supply voltage to the PLL
to be independently bypassed. Even if PLL usage is not required
VDDPLL and VSSPLL must be connected to properly.
A passive external loop filter must be placed on the XFC pin. The filter is
a second-order, low-pass filter to eliminate the VCO input ripple. The
value of the external filter network and the reference frequency
determines the speed of the corrections and the stability of the PLL. If
PLL usage is not required the XFC pin must be tied to VDDPLL.
MCU
XFC
VDDPLL
C_S
C_P
R_S
EXTAL, XTAL
Figure 41 PLL Loop Filter Connections
These pins provide the interface for either a crystal or a CMOS
compatible clock to control the internal clock generator circuitry. EXTAL
is the external clock input or the input to the crystal oscillator amplifier.
XTAL is the output of the crystal oscillator amplifier. All the MCU internal
system clocks are derived from the EXTAL input frequency.
MC9S12T64Revision 1.1.1
Clocks and Reset Generator (CRG)
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