MC9S12T64 Datasheet, PDF (381/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Register Descriptions
Output Compare 7
Data Register
(OC7D)
Register offset: $0043
Bit 7
Read:
OC7D7
Write:
Reset:
0
6
OC7D6
0
5
OC7D5
0
4
OC7D4
0
3
OC7D3
0
2
OC7D2
0
1
OC7D1
0
Bit 0
OC7D0
0
Read or write anytime.
A channel 7 output compare can cause bits in the output compare 7 data
register to transfer to the timer port data register depending on the output
compare 7 mask register.
Timer Count
Register (TCNT)
Register offset: $0044–$0045
Bit 15
14
13
12
11
10
Read: Bit 15
14
13
12
11
10
Write:
Bit 7
6
5
4
3
2
Read: Bit 7
6
5
4
3
2
Write:
Reset:
0
0
0
0
0
0
= Reserved or unimplemented
9
Bit 8
9
Bit 8
1
Bit 0
1
Bit 0
0
0
Read anytime.
Write has no meaning or effect in the normal mode; only writable in
special modes.
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle.
A separate read/write for high byte and low byte will give a different result
than accessing them as a word.
Enhanced Capture Timer (ECT)
For More Information On This Product,
Go to: www.freescale.com
MC9S12T64Revision 1.1.1