MC9S12T64 Datasheet, PDF (221/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Flash EEPROM 64K
Functional Description
PRDIV8 set to 0. The resulting FCLK is then 190kHz. As a result, the
Flash algorithm timings are increased over optimum target by:
(ù÷÷ – øĀ÷) ⁄ ù÷÷ × ø÷÷ = üì
NOTE:
WARNING:
Command execution time will increase proportionally with the period of
FCLK.
Because of the impact of clock synchronization on the accuracy of
the functional timings, programming or erasing the Flash cannot
be performed if the bus clock runs at less than 1 MHz.
Programming or erasing the Flash with an input clock < 150kHz
should be avoided. Setting FCLKDIV to a value such that FCLK <
150kHz can destroy the Flash due to overstress. Setting FCLKDIV
to a value such that (1/FCLK+1/(Bus Clock) ) < 5µs can result in
incomplete programming or erasure of the memory array cells.
If the FCLKDIV register is written, the bit FDIVLD is set automatically. If
this bit is zero, the register has not been written since the last reset.
Program and erase commands will not be executed if this register has
not been written to.
Flash EEPROM 64K
For More Information On This Product,
Go to: www.freescale.com
MC9S12T64Revision 1.1.1