MC9S12T64 Datasheet, PDF (39/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Instruction Set Overview
Table 4 Instruction Set Summary (Continued)
Source Form
BLE rel8
BLO rel8Same as BCS
BLS rel8
BLT rel8
BMI rel8
BNE rel8
BPL rel8
BRA rel8
BRCLR opr8a, msk8, rel8
BRCLR opr16a, msk8, rel8
BRCLR oprx0_xysppc, msk8, rel8
BRCLR oprx9,xysppc, msk8, rel8
BRCLR oprx16,xysppc, msk8, rel8
BRN rel8
BRSET opr8, msk8, rel8
BRSET opr16a, msk8, rel8
BRSET oprx0_xysppc, msk8, rel8
BRSET oprx9,xysppc, msk8, rel8
BRSET oprx16,xysppc, msk8, rel8
BSET opr8, msk8
BSET opr16a, msk8
BSET oprx0_xysppc, msk8
BSET oprx9,xysppc, msk8
BSET oprx16,xysppc, msk8
BSR rel8
BVC rel8
BVS rel8
CALL opr16a, page
CALL oprx0_xysppc, page
CALL oprx9,xysppc, page
CALL oprx16,xysppc, page
CALL [D,xysppc]
CALL [oprx16, xysppc]
CBA
CLCSame as ANDCC #$FE
CLISame as ANDCC #$EF
Operation
Branch if ≤ 0,signed; if Z | (N⊕V)=1,
then (PC)+2+rel⇒PC
Branch if lower, unsigned; if C=1,
then (PC)+2+rel⇒PC
Branch if lower or same, unsigned; if
C | Z=1, then (PC)+2+rel⇒PC
Branch if < 0, signed; if N⊕V=1, then
(PC)+2+rel⇒PC
Branch if minus; if N=1, then
(PC)+2+rel⇒PC
Branch if not equal to 0; if Z=0, then
(PC)+2+rel⇒PC
Branch if plus; if N=0, then
(PC)+2+rel⇒PC
Branch always
Address
Machine
Mode Coding (Hex)
REL
2F rr
REL
25 rr
REL
23 rr
REL
2D rr
REL
2B rr
REL
26 rr
REL
2A rr
REL
20 rr
Access Detail
PPP (branch)
P (no branch)
PPP (branch)
P (no branch)
PPP (branch)
P (no branch)
PPP (branch)
P (no branch)
PPP (branch)
P (no branch)
PPP (branch)
P (no branch)
PPP (branch)
P (no branch)
PPP
Branch if bit(s) clear; if
(M)•(mask byte)=0, then
(PC)+2+rel⇒PC
Branch never
DIR
EXT
IDX
IDX1
IDX2
REL
4F dd mm rr
rPPP
1F hh ll mm rr rfPPP
0F xb mm rr
rPPP
0F xb ff mm rr rfPPP
0F xb ee ff mm rr PrfPPP
21 rr
P
Branch if bit(s) set; if
(M)•(mask byte)=0, then
(PC)+2+rel⇒PC
Set bit(s) in M
(M) | mask byte⇒M
Branch to subroutine; (SP)–2⇒SP
RTN_H:RTN_L⇒M_SP:M_SP+1
(PC)+2+rel⇒PC
Branch if V clear; if V=0, then
(PC)+2+rel⇒PC
Branch if V set; if V=1, then
(PC)+2+rel⇒PC
Call subroutine in expanded memory
(SP)–2⇒SP
RTN_H:RTN_L⇒M_SP:M_SP+1
(SP)–1⇒SP; (PPG)⇒M_SP
pg⇒PPAGE register
subroutine address⇒PC
Compare A to B; (A)–(B)
DIR
EXT
IDX
IDX1
IDX2
DIR
EXT
IDX
IDX1
IDX2
REL
REL
REL
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
4E dd mm rr
rPPP
1E hh ll mm rr rfPPP
0E xb mm rr
rPPP
0E xb ff mm rr rfPPP
0E xb ee ff mm rr PrfPPP
4C dd mm
1C hh ll mm
0C xb mm
0C xb ff mm
0C xb ee ff mm
rPwO
rPwP
rPwO
rPwP
frPwPO
07 rr
SPPP
28 rr
29 rr
4A hh ll pg
4B xb pg
4B xb ff pg
4B xb ee ff pg
4B xb
4B xb ee ff
18 17
PPP (branch)
P (no branch)
PPP (branch)
P (no branch)
gnSsPPP
gnSsPPP
gnSsPPP
fgnSsPPP
fIignSsPPP
fIignSsPPP
OO
Clear C bit
Clear I bit
IMM
10 FE
P
IMM
10 EF
P
SXHINZVC
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Central Processing Unit (CPU)
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MC9S12T64Revision 1.1.1