MC9S12T64 Datasheet, PDF (335/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Pulse Width Modulator (PWM8B8C)
Register Descriptions
PWM Enable
Register (PWME)
Address Offset: $00A0
Bit 7
Read:
PWME7
Write:
Reset:
0
6
PWME6
0
5
PWME5
0
4
PWME4
0
3
PWME3
0
2
PWME2
0
1
PWME1
0
Bit 0
PWME0
0
Each PWM channel has an enable bit (PWMEx) to start its waveform
output. When any of the PWMEx bits are set (PWMEx=1), the
associated PWM output is enabled immediately. However, the actual
PWM waveform is not available on the associated PWM output until its
clock source begins its next cycle due to the synchronization of PWMEx
and the clock source.
The first PWM cycle after enabling the channel can be irregular.
An exception to this is when channels are concatenated. Once
concatenated mode is enabled (CONxx bits set in PWMCTL register)
then enabling/disabling the corresponding 16-bit PWM channel is
controlled by the low order PWMEx bit. In this case, the high order bytes
PWMEx bits have no effect and their corresponding PWM output lines
are disabled.
While in run mode, if all eight PWM channels are disabled PWMEx=0),
the prescaler counter shuts off for power savings.
Read: anytime
Write: anytime
PWME7 — Pulse Width Channel 7 Enable
1 = Pulse Width channel 7 is enabled. The pulse modulated signal
becomes available at PWM output bit7 when its clock source
begins its next cycle.
0 = Pulse Width channel 7 is disabled.
PWME6 — Pulse Width Channel 6 Enable
Pulse Width Modulator (PWM8B8C)
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MC9S12T64Revision 1.1.1