MC9S12T64 Datasheet, PDF (484/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
register will not be copied into the SPIDR register until after the slave SPI
has exited wait or stop mode. A SPIF flag and SPIDR copy is only
generated if wait mode is entered or exited during a transmission. If the
slave enters wait mode in idle mode and exits wait mode in idle mode,
neither a SPIF nor a SPIDR copy will occur.
SPI in Stop Mode
Stop mode is dependent on the system. The SPI enters stop mode when
the bus clock is disabled (held high or low). If the SPI is in master mode
and exchanging data when the CPU enters stop mode, the transmission
is frozen until the CPU exits stop mode. After stop, data to and from the
external SPI is exchanged correctly. In slave mode, the SPI will stay
synchronized with the master.
The stop mode is equivalent to the wait mode with the SPISWAI bit set
except that the stop mode is dependent on the system and cannot be
controlled with the SPISWAI bit.
Reset Initialization
The reset values of registers and signals are described in Registers. All
registers reset to a particular value.
• If a data transmission occurs in slave mode after reset without a
write to SPIDR, it will transmit random data or the byte last
received from the master before the reset.
• Reading from the SPIDR after reset will always read a byte of
zeros.
Interrupts
This section describes interrupts originated by the Serial Peripheral
Interface. The MCU must service the interrupt requests. Table 85 lists
the three sources of interrupts generated by the SPI module. The SPI
module communicates with the MCU through one interrupt port.
MC9S12T64Revision 1.1.1
Serial Peripheral Interface (SPI)
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