MC9S12T64 Datasheet, PDF (20/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
General Description
Features
• HCS12 Core
– 16-bit HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to
M68HC11
iii. 20-bit ALU
iv. Instruction queue
v. Enhanced indexed addressing
– MEBI (Multiplexed External Bus Interface) ¹
– MMC (Module Mapping Control)
– INT (Interrupt control)
– BKP (Breakpoints)
– FBDM (Fast Background Debug Mode)
i. Synchronous Serial Peripheral Interface (SPI mode) to
allow fast read and write of internal memory contents.
ii. 4M bit per second in SPI mode at 16MHz bus
iii. Single Wire Interface
• CRG (low current oscillator, PLL, reset, clocks, COP watchdog,
real time interrupt, clock monitor)
• LVD (Low Voltage Detector)
– Low Voltage Detector to pull reset when the V_DDR Supply
Voltage falls to LVD trip voltage.
• 64K byte Flash EEPROM ²
– Two 32K byte Flash EEPROM blocks independently
programmable and erasable
1. Internal Flash EEPROM must be disabled to connect external memory devices with the exter-
nal bus.
2. Whole 64K bytes of Flash EEPROM can not be used at a time, since 1K byte register block
and 2K byte RAM array are always overlapped with Flash EEPROM.
MC9S12T64Revision 1.1.1
General Description
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