MC9S12T64 Datasheet, PDF (107/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Operating Modes
Operating Modes
bus. After the system is running, application software can access the
PEAR and MODE registers to modify the expansion bus configuration.
Some aspects of Port E are not mode dependent. Bit 1 of Port E is a
general purpose input or the IRQ interrupt input. IRQ can be enabled by
bits in the CPUs condition codes register but it is inhibited at reset so this
pin is initially configured as a simple input with a pullup. Bit 0 of Port E is
a general purpose input or the XIRQ interrupt input. XIRQ can be
enabled by bits in the CPUs condition codes register but it is inhibited at
reset so this pin is initially configured as a simple input with a pullup. The
ESTR bit in the EBICTL register is set to one by reset in any user mode.
This assures that the reset vector can be fetched even if it is located in
an external slow memory device. The PE6/MODB/IPIPE1 and
PE5/MODA/IPIPE0 pins act as high-impedance mode select inputs
during reset.
The following paragraphs discuss the default bus setup and describe
which aspects of the bus can be changed after reset on a per mode
basis.
Normal Operating
Modes
These modes provide three operating configurations. Background
debug is available in all three modes, but must first be enabled for some
operations by means of a BDM background command, then activated.
Normal
Single-Chip Mode
There is no external expansion bus in this mode. All pins of Ports A, B
and K are configured as general purpose I/O pins. Port E bits 1 and 0 are
available as general purpose input only pins with internal pullups
enabled. All other pins of Port E are bidirectional I/O pins that are initially
configured as high-impedance inputs with internal pullups enabled.
The pins associated with Port E bits 7, 6, 5, 3, and 2 cannot be
configured for their alternate functions IPIPE1, IPIPE0, LSTRB, and R/W
while the MCU is in single chip modes. The associated control bits
PIPOE, LSTRE, and RDWE are reset to zero. Writing the opposite state
into them in single chip mode does not change the operation of the
associated Port E pins.
Operating Modes
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MC9S12T64Revision 1.1.1