MC9S12T64 Datasheet, PDF (475/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI)
Functional Description
Clock Phase and
Polarity Controls
Using two bits in the SPI control register1, software selects one of four
combinations of serial clock phase and polarity.
The CPOL clock polarity control bit specifies an active high or low clock
and has no significant effect on the transmission format.
The CPHA clock phase control bit selects one of two fundamentally
different transmission formats.
Clock phase and polarity should be identical for the master SPI device
and the communicating slave device. In some cases, the phase and
polarity are changed between transmissions to allow a master device to
communicate with peripheral slaves having different requirements.
NOTE:
It is recommended that software writes to the SPI control register to
change CPHA, CPOL or MSTR bits only in the idle state of the SPI. If
these bits are changed during the transmission, data transmission gets
corrupted.
CPHA = 0 Transfer
Format
The first edge on the SCK line is used to clock the first data bit of slave
into the master and the first data bit of master into the slave. In some
peripherals, the first bit of the slave's data is available at the slave data
out pin as soon as the slave is selected. In this format, the first SCK edge
is not issued until a half cycle into the 8-cycle transfer operation. The first
edge of SCK is delayed a half cycle by clearing the CPHA bit.
The SCK output from the master remains in the inactive state for a half
SCK period before the first edge appears. A half SCK cycle later, the
second edge appears on the SCK line. When this second edge occurs,
the value previously latched from the serial data input pin is shifted into
the LSB of the shifter.
After this second edge, the next bit of the SPI master data is transmitted
out of the serial data output pin of the master to the serial input pin on
the slave. This process continues for a total of 16 edges on the SCK line,
with data being latched on odd numbered edges and shifted on even
numbered edges.
Serial Peripheral Interface (SPI)
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MC9S12T64Revision 1.1.1