MC9S12T64 Datasheet, PDF (151/608 Pages) Motorola, Inc – Specification

Port E Register
(PORTE)
Freescale Semiconductor, Inc.
Multiplexed External Bus Interface (MEBI)
Register Descriptions
Address Offset: $0008
Bit 7
Read:
BIT 7
Write:
Reset:
Alt. Pin Function
XCLKS or
NOACC
6
5
4
3
6
5
4
3
Unaffected by reset
MODB or MODA or
IPIPE1 IPIPE0
ECLK
LSTRB or
TAGLO
= Unimplemented or reserved
2
BIT 2
R/W
1
BIT 1
IRQ
Bit 0
BIT 0
XIRQ
Read and write: anytime (provided this register is in the map).
Port E is associated with external bus control signals and interrupt
inputs. These include mode select (XCLKS/NOACC, MODB/IPIPE1,
MODA/IPIPE0), E clock, size (LSTRB/TAGLO), read / write (R/W),
IRQ, and XIRQ. When the associated pin is not used for one of these
specific functions, the Port E pins 7–2 can be used as general
purpose I/O and the Port E pins 1–0 can be used as general purpose
input. The Port E Assignment Register (PEAR) selects the function of
each pin and DDRE determines whether each pin is an input or output
when it is configured to be general purpose I/O. DDRE also
determines the source of data for a read of PORTE.
Some of these pins have software selectable pullups (PE7, ECLK,
LSTRB, R/W, IRQ and XIRQ). A single control bit enables the pullups
for all of these pins when they are configured as inputs.
This register is not in the on-chip map in peripheral mode or in
expanded modes when the EME bit is set.
CAUTION:
It is unwise to write PORTE and DRRE as a word access. If you are
changing PORT E pins from being inputs to outputs, the data may have
extra transitions during the write. It is best to initialize PORTE before
enabling as outputs.
CAUTION:
To ensure that you read the value present on the PORTE pins, always
wait at least two cycles after writing to the DDRE register before reading
from the PORTE register.
Multiplexed External Bus Interface (MEBI)
For More Information On This Product,
Go to: www.freescale.com
MC9S12T64Revision 1.1.1