MC9S12T64 Datasheet, PDF (348/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Pulse Width Modulator (PWM8B8C)
the PWMCNTx register. For more detailed information on the operation
of the counters, reference PWM Timer Counters.
In concatenated mode, writes to the 16-bit counter by using a 16-bit
access or writes to either the low or high order byte of the counter will
reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency
CAUTION: Writing to the counter while the channel is enabled can cause an
irregular PWM cycle to occur.
PWM Channel
Period Registers
(PWMPERx)
Where: x=0,1,2,3,4,5,6,7
Address Offset: $00B4, $00B5, $00B6,$00B7, $00B8, $00B9, $00BA, $00BB
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
1
1
1
1
1
1
1
1
Read: anytime
Write: anytime
There is a dedicated period register for each channel. The value in this
register determines the period of the associated PWM channel.
The period registers for each channel are double buffered so that if they
change while the channel is enabled, the change will NOT take effect
until one of the following occurs:
• The effective period ends
• The counter is written (counter resets to $00)
• The channel is disabled
In this way, the output of the PWM will always be either the old waveform
or the new waveform, not some variation in between. If the channel is
not enabled, then writes to the period register will go directly to the
latches as well as the buffer.
MC9S12T64Revision 1.1.1
Pulse Width Modulator (PWM8B8C)
For More Information On This Product,
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