MC9S12T64 Datasheet, PDF (147/608 Pages) Motorola, Inc – Specification

Port A Register
(PORTA)
Freescale Semiconductor, Inc.
Multiplexed External Bus Interface (MEBI)
Register Descriptions
Address Offset: $0000
Bit 7
Read:
BIT 7
Write:
Reset:
Single Chip:
PA7
Exp Wide, Emul
Nar with IVIS &
Periph:
ADDR15/
DATA15
Expanded
narrow
ADDR15/
DATA15/
DATA7
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
BIT 0
PA6
ADDR14/
DATA14
PA5
ADDR13/
DATA13
Unaffected by reset
PA4
PA3
ADDR12/ ADDR11/
DATA12 DATA11
PA2
ADDR10/
DATA10
PA1
ADDR9/
DATA9
PA0
ADDR8/
DATA8
ADDR14/
DATA14/
DATA6
ADDR13/
DATA13/
DATA5
ADDR12/
DATA12/
DATA4
ADDR11/
DATA11/
DATA3
ADDR10/
DATA10/
DATA2
ADDR9/
DATA9/
DATA1
ADDR8/
DATA8/
DATA0
Read and write: anytime (provided this register is in the map).
Port A bits 7 through 0 are associated with address lines A15 through
A8 respectively and data lines D15/D7 through D8/D0 respectively.
When this port is not used for external addresses such as in
single-chip mode, these pins can be used as general purpose I/O.
Data Direction Register A (DDRA) determines the primary direction of
each pin. DDRA also determines the source of data for a read of
PORTA.
This register is not in the on-chip map in expanded and peripheral
modes.
CAUTION:
To ensure that you read the value present on the PORTA pins, always
wait at least two cycles after writing to the DDRA register before
reading from the PORTA register.
Multiplexed External Bus Interface (MEBI)
For More Information On This Product,
Go to: www.freescale.com
MC9S12T64Revision 1.1.1