MC9S12T64 Datasheet, PDF (527/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Fast Background Debug Module (FBDM)
Register Descriptions
The secure BDM firmware lookup table verifies that the FLASH is
erased. This being the case, UNSEC signal is set. The BDM program
jumps to start of the standard BDM firmware lookup table and the
secure BDM firmware lookup table is turned off. If the erase test fails,
the UNSEC bit will not be asserted.
1 = the part is in the unsecured mode
0 = the part is in the secured mode
WARNING:
When UNSEC is set, security is off and the user can change the state of
the secure bits in the on-chip Flash EEPROM. Note that if the user does
not change the state of the bits to “unsecured” mode, the system will be
secured again when it is next taken out of reset.
BDM CCR Holding
Register
(BDMCCR)
Address: $FF06
Bit 7
Read:
CCR7
Write:
Reset:
0
6
CCR6
0
5
CCR5
0
4
CCR4
0
3
CCR3
0
2
CCR2
0
1
CCR1
0
Bit 0
CCR0
0
Read: All modes
Write: All modes
NOTE:
When BDM is made active, the CPU stores the value of the CCR register
in the BDMCCR register. However, out of special single-chip reset, the
BDMCCR is set to $D8 and not $D0 which is the reset value of the CCR
register.
CCR7–CCR0 — BDM CCR Holding Bits
When entering background debug mode, the BDM CCR holding
register is used to save the contents of the condition code register of
the user’s program. It is also used for temporary storage in the
standard BDM firmware mode. The BDM CCR holding register can be
written to modify the CCR value.
Fast Background Debug Module (FBDM)
For More Information On This Product,
Go to: www.freescale.com
MC9S12T64Revision 1.1.1