MC9S12T64 Datasheet, PDF (543/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Fast Background Debug Module (FBDM)
Functional Description
CLOCK
TARGET SYS.
HOST
DRIVE TO
BKGD PIN
TARGET SYS.
DRIVE AND
SPEEDUP PULSE
PERCEIVED
START OF BIT TIME
BKGD PIN
HIGH-IMPEDANCE
SPEEDUP PULSE
10 CYCLES
10 CYCLES
HOST SAMPLES
BKGD PIN
Figure 106 BDM Target-to-Host Serial Bit Timing (Logic 0)
EARLIEST
START OF
NEXT BIT
BDM Serial
Interface in SPI
mode
An eight bit transfer in SPI mode is shown in the diagram (see
Figure 107). The data is shifted (changes) on the falling edges of SCK
and it is sampled (registered) on the rising edges of SCK. The SCK clock
is always driven into the BDM and initiates a transfer. It’s idle state is
one. Commands, addresses and write data are driven into the BDM on
SI and read data is driven out of the BDM on SO.
SCK
SI
SO
MSB 6 5 4 3 2 1 LSB
MSB 6 5 4 3 2 1 LSB
DATA IS SHIFTED AT SCK FALLING EDGES AND SAMPLED AT SCK RISING EDGES
Figure 107 8-Bit Data Transfer in SPI Mode
Timing specifications for the SPI mode interface are described in the
table (see Table 100). SCK must be no faster than 4 target clocks. When
Fast Background Debug Module (FBDM)
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MC9S12T64Revision 1.1.1