MC9S12T64 Datasheet, PDF (511/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Analog to Digital Converter (ATD)
Functional Description
Read: Anytime
Write: Anytime, no effect.
The A/D conversion results are stored in 8 read-only result registers.
The result data is formatted in the result registers based on two
criteria. First there is left and right justification; this selection is made
using the DJM control bit in ATDCTL5. Second there is signed and
unsigned data; this selection is made using the DSGN control bit in
ATDCTL5. Signed data is stored in 2’s complement format and only
exists in left justified format. Signed data selected for right justified
format is ignored.
For 8-bit result data, the result data maps between the high (left
justified) and low (right justified) order bytes of the result register. For
10-bit result data, the result data maps between bits 6–15 (left
justified) and bits 0–9 (right justified) of the result register. Therefore
for each bit in the SAR, there are 3 possible mappings of this bit into
the result registers.
Functional Description
General
The ATD module is structured in an analog and a digital sub-block.
Analog Sub-block
The analog sub-block contains all analog electronics required to perform
a single conversion. Separate power supplies VDDA and VSSA allow to
isolate noise of other MCU circuitry from the analog sub-block.
Sample and Hold
Machine
The Sample and Hold (S/H) Machine accepts analog signals from the
external surroundings and stores them as capacitor charge on a storage
node.
The sample process uses a two stage approach. During the first stage,
the sample amplifier is used to quickly charge the storage node. The
second stage connects the input directly to the storage node to complete
the sample for high accuracy.
Analog to Digital Converter (ATD)
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MC9S12T64Revision 1.1.1