MC9S12T64 Datasheet, PDF (26/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Programming Model
The Core CPU12 programming model, shown in Figure 2, is the same as that of
the 68HC12 and 68HC11. The register set and data types used in the model are
covered in the subsections that follow.
7
A
15
15
15
15
15
07
B
0 8-BIT ACCUMULATORS A AND B
D
0 16-BIT DOUBLE ACCUMULATOR D (A: B)
X
0 INDEX REGISTER X
Y
0 INDEX REGISTER Y
SP
0 STACK POINTER
PC
0 PROGRAM COUNTER
S X H I N Z V C CONDITION CODE REGISTER
CARRY
OVERFLOW
ZERO
NEGATIVE
IRQ INTERRUPT MASK (DISABLE)
HALF-CARRY FOR BCD ARITHMETIC
XIRQ INTERRUPT MASK (DISABLE)
STOP DISABLE (IGNORE STOP INSTRUCTION)
Figure 2 Programming Model
Accumulators
General-purpose 8-bit accumulators A and B hold operands and results
of operations. Some instructions use the combined 8-bit accumulators,
A:B, as a 16-bit double accumulator, D, with the most significant byte in
A.
MC9S12T64Revision 1.1.1
Central Processing Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com