MC9S12T64 Datasheet, PDF (322/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Figure 56 and Figure 57 show the power-up sequence for cases when
the RESET pin is tied to VDD and when the RESET pin is held low. Note
that the reset sequence only starts after a running SYSCLK is detected.
RESET
Internal POR
Internal RESET
Clock Quality Check
(no Self-Clock Mode)
)(
)(
128 SYSCLK
)(
64 SYSCLK
Figure 56 RESET pin tied to VDD (by a pull-up resistor)
RESET
Internal POR
Internal RESET
Clock Quality Check
(no Self Clock Mode)
)(
)(
128 SYSCLK
)(
64 SYSCLK
Figure 57 RESET pin held low externally
NOTE: Proper function of the LVD module requires the voltage regulator to be
enable during operation (VREGEN pin tied high).
NOTE:
POR is only rearmed if the VDD voltage falls below the POR rearm level
(V_POR ¹).
There are four possible combinations of PORLVDRF (CRGFLG register)
and LVDF (LVDSR register) flags that can be obtained during operation.
1. See Table 116 in page 578 for the actual values of these parameters.
MC9S12T64Revision 1.1.1
Clocks and Reset Generator (CRG)
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