MC9S12T64 Datasheet, PDF (178/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Resets and Interrupts
Effects of Reset
When a reset occurs, MCU registers and control bits are changed to
known start-up states, as follows.
Operating Mode
and Memory Map
Operating mode and default memory mapping are determined by the
states of the BKGD, MODA, and MODB pins during reset. The MODA,
MODB, and MODC bits in the MODE register reflect the status of the
mode-select inputs at the rising edge of reset. Operating mode and
default maps can subsequently be changed according to strictly defined
rules.
Clock and
Watchdog Control
Logic
The COP watchdog system is enabled, with CR[2:0]=%011. The clock
monitor is enabled. The RTIF flag is cleared and the real time interrupt
is disabled. The RTR bits in the RTICTL are cleared, and must be
initialized before the RTI system is used.
Interrupts
PSEL is initialized in the HPRIO register with the value $F2, causing the
external IRQ pin to have the highest I-bit interrupt priority. The IRQ pin
is configured for level-sensitive operation. However, the interrupt mask
bits in the CPU12 CCR are set to mask X- and I-related interrupt
requests.
Parallel I/O
If the MCU comes out of reset in a single-chip mode, all ports are
configured as general-purpose high-impedance inputs.
If the MCU comes out of reset in an expanded mode, port A and port B
are used for the address/data bus, and port E pins are normally used to
control the external bus. Out of reset, port K, port E, port T, port S, port
P and port AD are all configured as general-purpose inputs.
Central Processing
Unit
After reset, the CPU fetches a vector from the appropriate address, then
begins executing instructions. The stack pointer and other CPU registers
are initialized immediately after reset. The CCR X and I interrupt mask
MC9S12T64Revision 1.1.1
Resets and Interrupts
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