MC9S12T64 Datasheet, PDF (535/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Fast Background Debug Module (FBDM)
Functional Description
BDM Command
Structure
Hardware and firmware BDM commands start with an 8-bit opcode
followed by a 16-bit address and/or a 16-bit data word depending on the
command. All the read commands return 16 bits of data despite the byte
or word implication in the command name.
NOTE:
8-bit reads return 16-bits of data, of which, only one byte will contain
valid data. If reading an even address, the valid data will appear in the
MSB. If reading an odd address, the valid data will appear in the LSB.
NOTE:
16-bit misaligned reads and writes are not allowed. If attempted, the
BDM module will ignore the least significant bit of the address and will
assume an even address from the remaining bits.
Hardware
Commands in
Single Wire Mode
For hardware data read commands, the external host must wait 150
target clock cycles¹ after sending the address before attempting to
obtain the read data. This is to be certain that valid data is available in
the BDM shift register, ready to be shifted out. For hardware write
commands, the external host must wait 150 target clock cycles after
sending the data to be written before attempting to send a new
command. This is to avoid disturbing the BDM shift register before the
write has been completed. The 150 target clock cycle delay in both
cases includes the maximum 128 cycle delay that can be incurred as the
BDM waits for a free cycle before stealing a cycle.
Hardware
Commands in SPI
Mode
For hardware data read commands, the external host must wait the
hardware delay after sending the address before attempting to obtain
the read data. This is to be certain that valid data is available in the BDM
shift register, ready to be shifted out. For hardware write commands, the
external host must wait the hardware delay after sending the data to be
written before attempting to send a new command. This is to avoid
disturbing the BDM shift register before the write has been completed.
Refer to Hardware Delay in SPI Mode in page 539.
1. Target clock cycles are cycles measured using the target system’s serial clock rate. See BDM
Serial Interface and BDM Status Register (BDMSTS) for information on how serial clock rate is
selected.
Fast Background Debug Module (FBDM)
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MC9S12T64Revision 1.1.1