MC9S12T64 Datasheet, PDF (406/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
8-Bit Pulse
Accumulators
Holding Registers
(PA3H–PA0H)
Register offset: $0072–$0075
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read: any time
Write: has no effect.
These registers are used to latch the value of the corresponding pulse
accumulator when the related bits in register ICPAR are enabled (see
Pulse Accumulators).
Modulus
Down-Counter
Count Register
(MCCNT)
Register offset: $0076–$0077
Bit 15
14
13
12
11
10
Read:
Bit 15
14
13
12
11
10
Write:
Bit 7
6
5
4
3
2
Read:
Bit 7
6
5
4
3
2
Write:
Reset:
1
1
1
1
1
1
= Reserved or unimplemented
9
8
9
Bit 8
1
Bit 0
1
Bit 0
1
1
Read or write any time.
A full access for the counter register should take place in one clock cycle.
A separate read/write for high byte and low byte will give different result
than accessing them as a word.
MC9S12T64Revision 1.1.1
Enhanced Capture Timer (ECT)
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