MC9S12T64 Datasheet, PDF (499/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Analog to Digital Converter (ATD)
Register Descriptions
ATD Control
Register 4
(ATDCTL4)
This register selects the conversion clock frequency, the length of the
second phase of the sample time and the resolution of the A/D
conversion (i.e.: 8-bits or 10-bits). Writes to this register will abort current
conversion sequence but will not start a new sequence.
Address Offset: $0084
Bit 7
Read:
SRES8
Write:
Reset:
0
6
5
4
3
2
1
Bit 0
SMP1
SMP0
PRS4
PRS3
PRS2
PRS1
PRS0
0
0
0
0
1
0
1
Unimplemented or Reserved
SRES8 — A/D Resolution Select
1 = 8-bit resolution selected.
0 = 10-bit resolution selected.
This bit selects the resolution of A/D conversion results as either 8 or
10 bits. The A/D converter has an accuracy of 10 bits. However, if low
resolution is required, the conversion can be speeded up by selecting
8-bit resolution.
SMP0, SMP1 — Sample Time Select
These two bits select the length of the second phase of the sample
time in units of ATD conversion clock cycles. Note that the ATD
conversion clock period is itself a function of the prescaler value (bits
PRS4-0). The sample time consists of two phases. The first phase is
two ATD conversion clock cycles long and transfers the sample
quickly (via the buffer amplifier) onto the A/D machine’s storage node.
The second phase attaches the external analog signal directly to the
storage node for final charging and high accuracy. Table 89 lists the
lengths available for the second sample phase.
Table 89 Sample Time Select
SMP1
0
0
1
1
SMP0
0
1
0
1
Length of Second Phase of Sample Time
2 A/D clock periods
4 A/D clock periods
8 A/D clock periods
16 A/D clock periods
Analog to Digital Converter (ATD)
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MC9S12T64Revision 1.1.1