MC9S12T64 Datasheet, PDF (46/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Table 4 Instruction Set Summary (Continued)
Source Form
Operation
Address
Machine
Mode Coding (Hex)
Access Detail
MOVW #oprx16, opr16a
Move word
IMM-EXT 18 03 jj kk hh ll OPWPO
MOVW #opr16i, oprx0_xysppc
Memory-to-memory 16-bit word-move IMM-IDX 18 00 xb jj kk OPPW
MOVW opr16a, opr16a
MOVW opr16a, oprx0_xysppc
(M₁:M₁+1)⇒M₂:M₂+1
EXT-EXT 18 04 hh ll hh ll ORPWPO
First operand specifies word to move ^{EXT-IDX 18 01 xb hh ll OPRPW}
MOVW oprx0_xysppc, opr16a
IDX-EXT 18 05 xb hh ll ORPWP
MOVW oprx0_xysppc, oprx0_xysppc
IDX-IDX 18 02 xb xb
ORPWO
MUL
Multiply, unsigned
INH
12
O
(A)×(B)⇒A:B; 8 by 8-bit
NEG opr16a
NEG oprx0_xysppc
NEG oprx9,xysppc
NEG oprx16,xysppc
NEG [D,xysppc]
NEG [oprx16,xysppc]
NEGA
NEGB
Negate M; 0–(M)⇒M or (M)+1⇒M
Negate A; 0–(A)⇒A or (A)+1⇒A
Negate B; 0–(B)⇒B or (B)+1⇒B
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
INH
INH
70 hh ll
60 xb
60 xb ff
60 xb ee ff
60 xb
60 xb ee ff
40
50
rPwO
rPw
rPwO
frPwP
fIfrPw
fIPrPw
O
O
NOP
No operation
INH
A7
O
ORAA #opr8i
ORAA opr8a
ORAA opr16a
ORAA oprx0_xysppc
ORAA oprx9,xysppc
ORAA oprx16,xysppc
ORAA [D,xysppc]
ORAA [oprx16,xysppc]
ORAB #opr8i
ORAB opr8a
ORAB opr16a
ORAB oprx0_xysppc
ORAB oprx9,xysppc
ORAB oprx16,xysppc
ORAB [D,xysppc]
ORAB [oprx16,xysppc]
ORCC #opr8i
OR accumulator A
(A) | (M)⇒A
or (A) | imm⇒A
OR accumulator B
(B) | (M)⇒B
or (B) | imm⇒B
OR CCR; (CCR) | imm⇒CCR
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
IMM
DIR
EXT
IDX
IDX1
IDX2
[D,IDX]
[IDX2]
IMM
8A ii
9A dd
BA hh ll
AA xb
AA xb ff
AA xb ee ff
AA xb
AA xb ee ff
CA ii
DA dd
FA hh ll
EA xb
EA xb ff
EA xb ee ff
EA xb
EA xb ee ff
14 ii
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
rPf
rPO
rPf
rPO
frPP
fIfrPf
fIPrPf
P
PSHA
PSHB
PSHC
PSHD
PSHX
PSHY
PULA
PULB
PULC
PULD
Push A; (SP)–1⇒SP; (A)⇒M_SP
INH
36
Os
Push B; (SP)–1⇒SP; (B)⇒M_SP
INH
37
Os
Push CCR; (SP)–1⇒SP;
INH
39
Os
(CCR)⇒M_SP
Push D
INH
3B
OS
(SP)–2⇒SP; (A:B)⇒M_SP:M_SP+1
Push X
INH
34
OS
(SP)–2⇒SP; (X_H:X_L)⇒M_SP:M_SP+1
Push Y
INH
35
OS
(SP)–2⇒SP; (Y_H:Y_L)⇒M_SP:M_SP+1
Pull A
INH
32
ufO
(M_SP)⇒A; (SP)+1⇒SP
Pull B
INH
33
ufO
(M_SP)⇒B; (SP)+1⇒SP
Pull CCR
INH
38
ufO
(M_SP)⇒CCR; (SP)+1⇒SP
Pull D
INH
3A
UfO
(M_SP:M_SP+1)⇒A:B; (SP)+2⇒SP
SXHINZVC
––––––––
–––––––∆
––––∆∆∆∆
––––––––
––––∆∆0–
––––∆∆0–
⇑^–⇑⇑⇑⇑⇑⇑
––––––––
––––––––
––––––––
––––––––
––––––––
––––––––
––––––––
––––––––
∆⇓∆∆∆∆∆∆
––––––––
MC9S12T64Revision 1.1.1
Central Processing Unit (CPU)
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