MC9S12T64 Datasheet, PDF (29/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Central Processing Unit (CPU)
Programming Model
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Figure 7 Stack Pointer (SP)
When an interrupt occurs, the CPU:
• Completes execution of the current instruction
• Calculates the address of the next instruction and pushes it onto
the stack
• Pushes the contents of all the CPU registers onto the stack
• Loads the program counter with the address pointed to by the
interrupt vector, and begins execution at that address
The stacked CPU registers are referred to as an interrupt stack frame.
The Core stack frame is the same as that of the CPU.
Program Counter
(PC)
PC is a 16-bit register that holds the address of the next instruction to be
executed. The address in PC is automatically incremented each time an
instruction is executed.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8 Program Counter (PC)
Condition Code
Register (CCR)
CCR has five status bits, two interrupt mask bits, and a STOP instruction
mask bit. It is named for the five conditions indicated by the status bits.
Central Processing Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
MC9S12T64Revision 1.1.1