MC9S12T64 Datasheet, PDF (206/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Flash EEPROM 64K
Register Descriptions
NOTE: All bits of all registers in this module are completely synchronous to
internal clocks during a register read.
FCLKDIV — Flash
Clock Divider
Register
The FCLKDIV register is used to control timed events in program and
erase algorithms. This register is unbanked.
Address Offset: $0100
Bit 7
Read: FDIVLD
Write:
Reset: 0
6
5
4
PRDIV8 FDIV5
FDIV4
0
0
0
= Reserved or unimplemented
3
FDIV3
0
2
FDIV2
0
1
FDIV1
0
Bit 0
FDIV0
0
Read: Anytime
Write: Once in normal mode, anytime in special mode
NOTE: Access to this register during Flash Super User mode (FSUM=1) will
cause the ACCERR bit set.
FDIVLD — Flash Clock Divider Loaded
1 = Register has been written to since the last reset.
0 = Register has not been written.
PRDIV8 — Enable Prescaler by 8
1 = Enables a prescaler by 8, to divide the Flash module input
oscillator clock before feeding into the FCLKDIV divider.
0 = The input oscillator clock is directly fed into the FCLKDIV
divider
FDIV[5:0] — Flash Clock Divider Bits
The combination of PRDIV8 and FDIV[5:0] effectively divides the
Flash module input oscillator clock down to a frequency of 150-200
KHz. The maximum divide ratio is 512. Table 35 show some
FCLKDIV settings. Please refer to Writing the FCLKDIV Register in
page 220 for details about how to calculate these values.
MC9S12T64Revision 1.1.1
Flash EEPROM 64K
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