MC9S12T64 Datasheet, PDF (304/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
If PCE bit is set, the COP will continue to run in Pseudo-Stop Mode.
Real Time Interrupt
(RTI)
The RTI can be used to generate a hardware interrupt at a fixed periodic
rate. If enabled (by setting RTIE=1), this interrupt will occur at the rate
selected by the RTICTL register. The RTI runs with a gated OSCCLK
(see Figure 52). At the end of the RTI time-out period the RTIF flag is set
to one and a new RTI time-out period starts immediately.
A write to the RTICTL register restarts the RTI time-out period.
If the PRE bit is set, the RTI will continue to run in Pseudo-Stop Mode.
WAIT(RTIWAI),
STOP(PSTP,PRE),
RTI enable
OSCCLK
÷ 1024
RTR[6:4]
0:0:0
gating condition
= Clock Gate
0:0:1
÷2
0:1:0
÷2
0:1:1
÷2
1:0:0
÷2
1:0:1
÷2
1:1:0
÷2
1:1:1
4-BIT MODULUS
RTI TIMEOUT
COUNTER (RTR[3:0])
Figure 52 Clock Chain for RTI
MC9S12T64Revision 1.1.1
Clocks and Reset Generator (CRG)
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