MC9S12T64 Datasheet, PDF (495/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Analog to Digital Converter (ATD)
Register Descriptions
When entering Wait Mode this bit provides on/off control over the ATD
module block allowing reduced MCU power. Because analog
electronic is turned off when powered down, the ATD requires a
recovery time period after exit from Wait mode.
1 = Power down ATD during Wait mode
0 = ATD continues to run in Wait mode
NOTE:
Although a conversion that was interrupted prior to entering WAIT mode
is restarted after WAIT mode wake-up, the results are not reliable and
should not be used by the user application.
ETRIGLE — External Trigger Level/Edge Control
This bit controls the sensitivity of the external trigger signal. See Table
86 for details.
ETRIGP — External Trigger Polarity
This bit controls the polarity of the external trigger signal. See Table
86 for details.
Table 86 External Trigger Configurations
ETRIGLE
0
0
1
1
ETRIGP
0
1
0
1
External Trigger
Sensitivity
falling edge
rising edge
low level
high level
ETRIGE — External Trigger Mode Enable
This bit enables the external trigger on ATD channel 7. The external
trigger allows to synchronize sample and ATD conversions processes
with external events.
1 = Enable external trigger
0 = Disable external trigger
NOTE: The conversion results for the external trigger ATD channel 7 have no
meaning while external trigger mode is enabled.
ASCIE — ATD Sequence Complete Interrupt Enable
Analog to Digital Converter (ATD)
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MC9S12T64Revision 1.1.1