MC9S12T64 Datasheet, PDF (320/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
RESET
SYSCLK
)(
)(
CRG drives RESET pin low
RESET pin
released
)
)
)
(
(
(
eventually
SYSCLK
not
running
128+n cycles
with n being
min 3 / max 4
cycles depending
on internal
synchronization
delay
64 cycles
eventually
RESET
driven low
externally
Figure 55 RESET Timing
Clock Monitor
Reset
The CRG generates a Clock Monitor Reset in case all of the following
conditions are true:
• Clock monitor is enabled (CME=1)
• Loss of clock is detected
• Self-Clock Mode is disabled (SCME=0).
The reset event asynchronously forces the configuration registers to
their default settings (see Register Descriptions in page 280). In detail
the CME and the SCME are reset to logical “1” (which doesn’t change
the state of the CME bit, because it has already been set). As a
consequence the CRG immediately enters Self Clock Mode and starts
its internal reset sequence. The clock quality check starts in parallel. As
soon as the clock quality check indicates a valid OSCCLK, CRG
switches to OSCCLK and leaves Self Clock Mode. Since the clock
quality checker is running in parallel to the reset generator, the CRG may
leave Self Clock Mode while still completing the internal reset sequence,
e.g. when a high frequency OSCCLK is provided. When the reset
sequence is finished the CRG checks the internally latched state of the
clock monitor fail circuit. If a clock monitor fail is indicated processing
begins by fetching the Clock Monitor Reset vector.
MC9S12T64Revision 1.1.1
Clocks and Reset Generator (CRG)
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