MC9S12T64 Datasheet, PDF (343/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Pulse Width Modulator (PWM8B8C)
Register Descriptions
CAE2 — Center Aligned Output Mode on channel 2
1 = Channel 2 operates in Center Aligned Output Mode.
0 = Channel 2 operates in Left Aligned Output Mode.
CAE1 — Center Aligned Output Mode on channel 1
1 = Channel 1 operates in Center Aligned Output Mode.
0 = Channel 1 operates in Left Aligned Output Mode.
CAE0 — Center Aligned Output Mode on channel 0
1 = Channel 0 operates in Center Aligned Output Mode.
0 = Channel 0 operates in Left Aligned Output Mode.
PWM Control
Register (PWMCTL)
Address Offset: $00A5
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
CON67
CON45
CON23
CON01
PSWAI
PFRZ
Write:
Reset:
0
0
0
0
0
0
0
0
The PWMCTL register provides for various control of the PWM module.
Read: anytime
Write: anytime
There are three control bits for concatenation, each of which is used to
concatenate a pair of PWM channels into one 16-bit channel. When
channels 6 and 7 are concatenated, channel 6 registers become the
high order bytes of the double byte channel as shown in Figure 66.
Similarly, when channels 4 and 5 are concatenated, channel 4 registers
become the high order bytes of the double byte channel. When channels
2 and 3 are concatenated, channel 2 registers become the high order
bytes of the double byte channel. When channels 0 and 1 are
concatenated, channel 0 registers become the high order bytes of the
double byte channel.
Reference PWM 16-Bit Functions for a more detailed description of the
concatenation PWM Function.
Pulse Width Modulator (PWM8B8C)
For More Information On This Product,
Go to: www.freescale.com
MC9S12T64Revision 1.1.1