MC9S12T64 Datasheet, PDF (526/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Fast Background Debug Module (FBDM)
TRACE — TRACE1 BDM firmware command is being executed
This bit gets set when a BDM TRACE1 firmware command is first
recognized. It will stay set as long as continuous back-to-back
TRACE1 commands are executed. This bit will get cleared when the
next command that is not a TRACE1 command is recognized.
1 = TRACE1 command is being executed
0 = TRACE1 command is not being executed
CLKSW — Clock switch
The CLKSW bit controls which clock the BDM operates with. It is only
writable from a hardware BDM command. A WRITE_BD_BYTE
command to address $FF01 changes the CLKSW bit. The 150 cycle
delay at the clock speed that is active during the data portion of the
command will occur before the new clock source is guaranteed to be
active. The start of the next BDM command uses the new clock for
timing subsequent BDM communications. This clock is referred as
target clock in this document.
1 = BDM system operates with bus clock rate
0 = BDM system operates with oscillator clock divided by 2 when
the PLLSEL bit is set, otherwise BDM system operates with
bus clock rate.
Table 97 Target Clock Selection Summary
CLKSW
0
0
1
PLLSEL
0
1
—
Target Clock
Bus Clock
Oscillator Clock / 2
Bus Clock
UNSEC — Unsecure
This bit is writable only in special single chip mode from the BDM
secure firmware and always resets to 0. This bit is clear as secured
mode is entered so that the secure BDM firmware lookup table is
enabled and put into the memory map along with the standard BDM
firmware lookup table.
MC9S12T64Revision 1.1.1
Fast Background Debug Module (FBDM)
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