MC9S12T64 Datasheet, PDF (155/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Multiplexed External Bus Interface (MEBI)
Register Descriptions
LSTRE — Low Strobe (LSTRB) Enable
Normal: write once
Emulation: write never
Special: write anytime.
1 = The associated pin (Port E bit 3) is configured as the LSTRB
bus control output. If BDM tagging is enabled, TAGLO is
multiplexed in on the rising edge of ECLK and LSTRB is driven
out on the falling edge of ECLK.
0 = The associated pin (Port E bit 3) is a general purpose I/O pin.
This bit has no effect in single chip, peripheral or normal expanded
narrow modes.
NOTE:
LSTRB is used during external writes. After reset in normal expanded
mode, LSTRB is disabled to provide an extra I/O pin. If LSTRB is
needed, it should be enabled before any external writes. External reads
do not normally need LSTRB because all 16 data bits can be driven even
if the MCU only needs 8 bits of data
RDWE — Read / Write Enable
Normal: write once
Emulation: write never
Special: write anytime
1 = The associated pin (Port E bit 2) is configured as the R/W pin.
0 = The associated pin (Port E bit 2) is a general purpose I/O pin.
This bit has no effect in single chip or peripheral modes.
NOTE:
R/W is used for external writes. After reset in normal expanded mode,
R/W is disabled to provide an extra I/O pin. If R/W is needed it should be
enabled before any external writes.
Multiplexed External Bus Interface (MEBI)
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MC9S12T64Revision 1.1.1