MC9S12T64 Datasheet, PDF (390/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Set when 16-bit free-running timer overflows from $FFFF to $0000.
This bit is cleared automatically by a write to the TFLG2 register with
bit 7 set. (See also TCRE control bit explanation in TSCR2 register -
page 387.)
Timer Input
Capture/Output
Compare
Registers 0–7
(TC0–TC7)
Register offset: $0050–$005F
Bit 7
6
5
4
3
2
Read:
Bit 7
6
5
4
3
2
Write:
Bit 15
14
13
12
11
10
Read:
Bit 15
14
13
12
11
10
Write:
Reset:
0
0
0
0
0
0
1
Bit 0
1
Bit 0
9
Bit 8
9
Bit 8
0
0
Read anytime.
Write anytime for output compare function. Writes to these registers
have no meaning or effect during input capture. All timer input
capture/output compare registers are reset to $0000.
Depending on the TIOS bit for the corresponding channel, these
registers are used to latch the value of the free-running counter when a
defined transition is sensed by the corresponding input capture edge
detector or to trigger an output action for output compare.
MC9S12T64Revision 1.1.1
Enhanced Capture Timer (ECT)
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