MC9S12T64 Datasheet, PDF (405/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
Register Descriptions
NOTE:
The input capture edge circuits of the 16-bit pulse accumulator PACB
are configured with control bits EDG0B and EDG0A in the TCTL4
register (see page 386).
Pulse Accumulator
B Flag Register
(PBFLG)
Register offset: $0071
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
0
PBOVF
Write:
Reset:
0
0
0
0
0
0
0
0
= Reserved or unimplemented
Read or write any time.
PBOVF — Pulse Accumulator B Overflow Flag
This bit is set when the 16-bit pulse accumulator B overflows from
$FFFF to $0000, or when 8-bit pulse accumulator 1 (PAC1) overflows
from $FF to $00.
This bit is cleared by a write to the PBFLG register with bit 1 set.
Any access to the PACN1 and PACN0 registers will clear the PBOVF
flag in this register when TFFCA bit in register TSCR1 (see page 382)
is set.
When PACMX=1 in ICSYS (see page 401), PBOVF bit can also be
set if 8-bit pulse accumulator 1 (PAC1) reaches $FF and followed an
active edge comes on PT1.
Enhanced Capture Timer (ECT)
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MC9S12T64Revision 1.1.1