MC9S12T64 Datasheet, PDF (307/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Low Power Options
Core req’s
Wait Mode.
PLLWAI=1
no
?
yes
Clear PLLSEL,
Disable PLL
CWAI or
SYSWAI=1
?
yes
Disable
core clocks
no
no
SYSWAI=1
?
yes
Disable
system clocks
Enter
Wait Mode
Wait Mode left
due to external reset
Exit Wait w.
ext.RESET
CME=1
no
?
yes
no
CM fail
?
yes
Exit Wait w. ^no
CMR
SCME=1
?
yes
Generate
SCM Interrupt
(Wakeup from Wait)
no
SCMIE=1
?
yes
Exit
Wait Mode
Enter
SCM
no
INT
?
yes
Exit
Wait Mode
no
SCM=1
?
yes
Enter
SCM
Continue w.
normal OP
Figure 53 Wait Mode Entry/Exit Sequence
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1