MC9S12T64 Datasheet, PDF (396/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Enhanced Capture Timer (ECT)
16–Bit Modulus
Down-Counter
Control Register
(MCCTL)
Register offset: $0066
Bit 7
Read:
Write:
MCZI
Reset:
0
6
5
4
MODMC RDMCL
0
ICLAT
0
0
0
= Reserved or unimplemented
3
0
FLMC
0
2
MCEN
0
1
MCPR1
0
Bit 0
MCPR0
0
Read or write any time except for bit 4.
MCZI — Modulus Counter Underflow Interrupt Enable
1 = Modulus counter interrupt is enabled.
0 = Modulus counter interrupt is disabled.
MODMC — Modulus Mode Enable
1 = Modulus mode is enabled. When the counter reaches $0000,
the counter is loaded with the latest value written to the
modulus count register.
0 = The counter counts once from the value written to it and will
stop at $0000.
NOTE: For proper operation, the MCEN bit should be cleared before modifying
the MODMC bit in order to reset the modulus counter to $FFFF.
RDMCL — Read Modulus Down-Counter Load
1 = Reads of the modulus count register will return the contents of
the load register.
0 = Reads of the modulus count register will return the present
value of the count register.
ICLAT — Input Capture Force Latch Action
When input capture latch mode is enabled - LATQ and BUFEN bit in
ICSYS (see page 401) are set - a write one to this bit immediately
forces the contents of the input capture registers TC0 to TC3 and their
MC9S12T64Revision 1.1.1
Enhanced Capture Timer (ECT)
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