MC9S12T64 Datasheet, PDF (319/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Reset Description
depending on the internal synchronization latency. After 128+n SYSCLK
cycles the RESET pin is released. The reset generator circuit of the CRG
waits for additional 64 SYSCLK cycles and then samples the RESET pin
to determine the originating source. Table 57 shows which vector will be
fetched.
Table 57 Reset Vector Selection
Sampled RESET
pin (64 SYSCLK
cycles after
release)
Clock Monitor
Reset pending
COP Reset
pending
1
0
0
1
1
X
1
0
1
0
X
X
Vector fetch
POR / LVDR /
External Reset
Clock Monitor
Reset
COP Reset
POR / LVDR /
External Reset
with rise of
RESET pin
NOTE:
External circuitry connected to the RESET pin should not include a large
capacitance that would interfere with the ability of this signal to rise to a
valid logic one within 64 SYSCLK cycles after the low drive is released.
The internal reset of the MCU remains asserted while the reset
generator completes the 192 SYSCLK long reset sequence. The reset
generator circuitry always makes sure the internal reset is negated
synchronously after completion of the 192 SYSCLK cycles. In case the
RESET pin is externally driven low for more than these 192 SYSCLK
cycles (External Reset), the internal reset remains asserted too.
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1