MC9S12T64 Datasheet, PDF (166/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Multiplexed External Bus Interface (MEBI)
The execution-start status signals are delayed by one E clock cycle to
allow a lagging program fetch and queue advance. Therefore the
execution-start status always refers to the data in stage three of the
queue.
The advance and load from bus signal can be used as a load-enable to
capture the instruction word on the data bus. This signal is effectively the
queue advance signal inside the CPU. Program data is registered into
stage one on the rising edge of t4 when queue advance is asserted.
No Movement
(0:0)
The 0:0 state at the falling edge of E indicates that there is no data
movement in the instruction queue during the current cycle. The 0:0
state at the rising edge of E indicates continuation of an instruction or
interrupt sequence during the previous cycle.
ALD — Advance
and Load from
Data Bus (1:0)
The three-stage instruction queue is advanced by one word and stage
one is refilled with a word of program information from the data bus. The
CPU requested the information two bus cycles earlier but, due to access
delays, the information was not available until the E cycle immediately
prior to the ALD.
INT — Start
Interrupt (0:1)
This state indicates program flow has changed to an interrupt sequence.
Normally this cycle is a read of the interrupt vector. However, in systems
that have interrupt vectors in external memory and an 8-bit data bus, this
cycle reads only the lower byte of the 16-bit interrupt vector.
SEV — Start Even
Instruction (1:0)
This state indicates that the instruction is in the even (high) half of the
word in stage three of the instruction queue. The queue treats the $18
prebyte of an instruction on page two of the opcode map as a special
one-byte, one-cycle instruction. However, interrupts are not recognized
at the boundary between the prebyte and the rest of the instruction.
SOD — Start Odd
Instruction (1:1)
This state indicates that the instruction in the odd (low) half of the word
in stage three of the instruction queue. The queue treats the $18 prebyte
of an instruction on page two of the opcode map as a special one-byte,
one-cycle instruction. However, interrupts are not recognized at the
boundary between the prebyte and the rest of the instruction.
MC9S12T64Revision 1.1.1
Multiplexed External Bus Interface (MEBI)
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