MC9S12T64 Datasheet, PDF (283/608 Pages) Motorola, Inc – Specification

Freescale Semiconductor, Inc.
Clocks and Reset Generator (CRG)
Register Descriptions
SCMIF — Self-clock mode Interrupt Flag
SCMIF is set to 1 when SCM status bit changes. This flag can only be
cleared by writing a 1. Writing a 0 has no effect. If enabled
(SCMIE=1), SCMIF causes an interrupt request.
1 = SCM condition has changed, either entered or exited self-clock
mode.
0 = No change in SCM bit.
SCM — Self-clock mode Status Bit
SCM reflects the current clocking mode. Writes have no effect.
1 = MCU is operating in Self Clock Mode with OSCCLK in an
unknown state. All clocks are derived from PLLCLK running at
its minimum frequency f_SCM. See Table 118 in page 582 for
the actual value of this parameter.
0 = MCU is operating normally with OSCCLK available.
CRG Interrupt
Enable Register
(CRGINT)
This register enables CRG interrupt requests.
Address Offset: $0038
Bit 7
6
Read:
0
RTIE
Write:
Reset:
0
0
5
4
3
0
0
LOCKIE
0
0
0
2
1
0
0
0
SCMIE
0
0
0
Read: anytime
Write: anytime.
RTIE — Real Time Interrupt Enable Bit
1 = Interrupt will be requested whenever RTIF is set.
0 = Interrupt requests from RTI are disabled.
LOCKIE — Lock Interrupt Enable Bit
1 = Interrupt will be requested whenever LOCKIF is set.
0 = LOCK interrupt requests are disabled.
Clocks and Reset Generator (CRG)
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MC9S12T64Revision 1.1.1